Page 388 - 완) I MDP 프로젝트 작품 보고서(전체과 1학년)1.6

play_time<=0;
addr<=0;
end
end
end

endmodule
//////////////////////////////////////////////////////////
module PWM(clk,reset,lamp,CDS,mode,phase,lp);//랭프 밝기 조절
input clk,reset;
input [7:0]CDS;
input phase;
input mode;
output lamp;
output [1:0]lp;
reg [1:0]current_state;
reg [31:0] spd_cl;
reg [31:0] counter;
reg [31:0] clk_dbun;
reg [7:0] sw_buff;
reg [1:0] lp;
reg [1:0]help;
assign lamp=(counter>spd_cl)? 1 : 0 ;//램프 밝기 변환

always @ (posedge clk, negedge reset)//채터링
begin
if(!reset)
sw_buff<=0;
else
sw_buff<={sw_buff,phase};
end

// pwm주파수
always @ (posedge clk,negedge reset)
begin
if(!reset) spd_cl<=0;
else
begin
if(spd_cl==500000) spd_cl<=0;
else spd_cl<=spd_cl+1;
end

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