Page 785 - 완) I MDP 프로젝트 작품 보고서(전체과 1학년)1.6

end

// 5ms 발생 회로
always @ (posedge clk, negedge reset)
begin
if(!reset)
cnt_clk <= 0;
else
begin
if(cnt_clk == 249999)
cnt_clk <= 1'b0;
else
cnt_clk <= cnt_clk+1'b1;
end
end

// 100ms 발생 회로
always @ (posedge clk, negedge reset)
begin
if(!reset)
cnt_100ms <= 0;
else
begin
if(state == delay_100ms)
begin
if(cnt_clk == 249999)
begin
if(cnt_100ms == 19) //5ms * 20
cnt_100ms <= 1'b0;
else
cnt_100ms <= cnt_100ms+1'b1;
end
end
else
cnt_100ms<=0;
end
end

// 50ms 발생 회로
always @ (posedge clk, negedge reset)
begin

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