Page 1106 - 3-2

output tx_out;
output [4:0]tx_cnt_state;

reg clk_uart; //9600bps flag
reg [19:0]clk_count; // 속도를 맞추기위한 카운트변수 (5625)
reg [7:0]tx_reg,tx_data;// 송신 데이터보관 변수
reg tx_empty; // 송신완료유무
reg [4:0]tx_cnt; // 비트의 길이
reg tx_out; // 출력
reg tx_flag=0;

parameter BAUD_CLK=16'd5208;//9600
assign tx_cnt_state=tx_cnt;

always@(posedge clk,negedge rst) //9600bps 속도에 맞게 분주
begin
if(!rst) begin clk_count<=0; clk_uart<=0; end
else
begin
if(clk_count==BAUD_CLK-1)
begin
clk_count<=0;
clk_uart<=1;
end
else
begin
clk_count<=clk_count+1;
clk_uart<=0;
end
end
end

always@(posedge clk,negedge rst)
begin
if(!rst)
begin
tx_empty<=1;
tx_out<=1;
tx_cnt<=0;
tx_flag<=0;
end
else
begin
if(flag) tx_flag<=1; //flag 로 송신 시작
if(clk_uart==1&&tx_flag==1) // 송신 모듈
begin
tx_data<=rx_input;
tx_empty<=0;

if(!tx_empty)
begin
tx_cnt<=tx_cnt+1;
if(tx_cnt==0) tx_out<=0;//start bit
if(tx_cnt>0&&tx_cnt<9) tx_out<=tx_data[tx_cnt-1]; // 데이타 전송
if(tx_cnt==9)
begin
tx_empty<=1;
tx_out<=1; //stop bit
tx_cnt<=0;
tx_flag<=0;
end
end
end
end
end
endmodule

module speaker_motor(clk,rst,l_sen_f,r_sen_f,motor,en);

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