Page 194 - MDP2020-2

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188

else
begin
vcc <= 1;
end
end

endmodule
*/
/*
module mdp1(clk, rst, led);
input clk, rst;
output reg [7:0] led;
reg clk_div;
reg [31:0] clk_cnt;
parameter DIV = 50000000;
always @(posedge clk, negedge rst)
begin
if(!rst)
begin
clk_cnt <= 0;
clk_div <= 0;
end
else
begin
if(clk_cnt >= DIV/2 - 1)
begin

clk_cnt <= 0;
clk_div <= 1;
end
else
begin
clk_cnt <= clk_cnt + 1;
clk_div <= 0;
end
end
end
always @(posedge clk, negedge rst)
begin
if(!rst)
begin
led <= 8'h55;
end
else
begin
if(clk_div == 1)