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rx_bit_cnt <= rx_bit_cnt + 1;
rx_en <= 0;
end

else if (rx_bit_cnt == 8 && rx_clk_cnt == CLOCKS_PER_BIT && uart_rxd == 1) // 스탑비
트 받은 경우
begin
rx_bit_cnt <= 0;
data[cnt] <= rx_data;
cnt <= (cnt+1)%2;
rx_en <= 1;
end

else if (rx_bit_cnt == 8 && rx_clk_cnt == CLOCKS_PER_BIT && uart_rxd != 1) // 스탑비트
못받을 경우
begin
rx_bit_cnt <= 0;
rx_data <= 8'b00000000; // invalidate
rx_en <= 0;
end
end
end

always @(posedge clk, negedge reset) //state_rx
if(!reset) state_rx <=0;
else
begin
if (rx_bit_cnt == 0 && uart_rxd == 0 && start_cnt == CLOCKS_WAIT_FOR_RECEIVE) state_rx <= 1;
else if (state_rx == 1)
begin
if (rx_bit_cnt == 8 && rx_clk_cnt == CLOCKS_PER_BIT && uart_rxd == 1) state_rx <= 0;
else if (rx_bit_cnt == 8 && rx_clk_cnt == CLOCKS_PER_BIT && uart_rxd != 1) state_rx
<= 0;
end
end

always@(posedge clk, negedge reset)
if(!reset) rx_en_buffer <= 2'b00;
else
begin
rx_en_buffer <= {rx_en_buffer[0],rx_en};
end

// 송신부
reg clk_uart;

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