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reg [15:0]clk_count;
reg [7:0]tx_reg;
reg tx_empty;
reg [3:0]tx_cnt;
reg uart_txd;
reg [7:0]sw_buff;
reg s_cnt = 0;
reg [7:0]string[1:0];
reg [30:0]rst_cnt;
reg rst_flag;

parameter BAUD_clk = 5208;

always @ (posedge clk, negedge reset)
if(!reset) begin string[0]<=8'h00; string[1] <= 8'h00; end
else
begin
string[0] <= data[1];
string[1] <= data[0];
end
always @(posedge clk, negedge reset)
if(!reset) begin clk_count <=0; clk_uart <=0; end
else
begin
if(clk_count == BAUD_clk-1)
begin
clk_count<=0;
clk_uart<=1;
end
else
begin
clk_count<=clk_count+1;
clk_uart<=0;
end
end

always @ (posedge clk, negedge reset) //tx_cnt
if(!reset) tx_cnt <=0;
else
begin
if(clk_uart==1)
begin
if(!tx_empty)
begin
if(tx_cnt==9) tx_cnt <=0;

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