Page 628 - 3-2

0: step_phase<=B_bar;
endcase
end
end
end
end
endmodule

[motor_push]
module motor_push(clk,reset,segnal,motor_dc);
input clk,reset,segnal;
output reg motor_dc;
reg time_cnt;
always @ (posedge clk, negedge reset)
begin
if(!reset)
motor_dc<=0;
else
begin
if(segnal) motor_dc<=1;
else motor_dc<=0;
end
end
endmodule

[motor_step]
module motor_step(clk,reset,DIR,STP,EN,VCC);
input clk, reset;
output reg STP;
output VCC;
output DIR,EN;
reg [30:0] cnt;
assign VCC = 1;
assign EN = (!reset)? 1: 0;
assign DIR = 1;
always @ (posedge clk ,negedge reset)
begin
if(!reset)
cnt<=0;
else
begin
if(cnt==675000)
begin
if(STP==1)
STP<=0;

- 628 -