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9. 소프트웨어 작성하기
가. FPGA 관련 소스
1) 탑 Module
module pro(clk,reset,sw1,sw2,liml,limr,limt,limb,dcmotor1,dcmotor2,dcmotor3
,led,uart_rxd,sig,sig_f,tx_out,lim);
input clk,reset;
input sw1,sw2;
input liml,limr,limt,limb;
input uart_rxd;// 수신선
input [5:0]lim;
output tx_out;//tx: 송신단자
output sig_f;
output [1:0]dcmotor1,dcmotor2;
output [1:0]dcmotor3;
output [3:0] led;
output sig;

wire [3:0]state;
wire [7:0]rx_data;
wire [7:0]var2;

tmotoru0(.clk(clk),.rst(reset),.dcmotor1(dcmotor1),.dcmotor2(dcmotor2),.dcmotor3(dcmotor3)
,.sw1(sw1),.sw2(sw2),.liml(liml),.limr(limr),.limt(limt),.limb(limb),.rx_data(rx_data)
,.sig(sig),.sig_f(sig_f),.state(state),.led(led));

uart_rxu1(.clk(clk),.reset(reset), .uart_rxd(uart_rxd),.rx_data(rx_data),.state(state));

uart_tx u2 (.clk(clk),.reset(reset),.tx_out(tx_out),.var2(var2));

balloon_num u3(.clk(clk),.reset(reset),.lim(lim),.var2(var2));

endmodule

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2) 하위 Module
A.NFC 신호를 받아 limit sw, sw 및 dcmotor 처리하는 소스
module tmotor (clk,rst,dcmotor1,dcmotor2,dcmotor3,sw1,sw2,liml,limr,limt,limb
,rx_data,sig,sig_f,state,led);

input [7:0]rx_data;
input clk,rst;
input sw1,sw2;
input liml,limr,limt,limb;
output reg [1:0]dcmotor1,dcmotor2;
output reg sig=0;

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