Page 202 - MDP2020-2
P. 202

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                                    cnt_100ms  <=  cnt_100ms;
                                end
                            end
                        else
                            begin
                              cnt_100ms  <=  0;                     //  delay_100ms
                            end
                      end
                end
              //20ms
              always  @(posedge  clk,  negedge  rst)
                begin
                    if(!rst)
                      begin
                        cnt_20ms  <=  0;
                      end
                    else
                      begin
                        if(state  ==  delay_20ms)   //  delay_20ms대
                            begin
                              if(clk_cnt  >=  DIV  -  1) //5ms
                                begin
                                  if(cnt_20ms  ==  3)       //5ms  x  4  =  20ms
                                      begin
                                        cnt_20ms  <=  0;
                                      end

                                    else
                                      begin
                                        cnt_20ms  <=  cnt_20ms  +  1;
                                      end
                                end
                              else
                                begin
                                    cnt_20ms  <=  cnt_20ms;
                                end
                            end
                        else
                            begin
                              cnt_20ms  <=  0;                      //delay_20ms
                            end
                      end
                end


              always  @(posedge  clk,  negedge  rst)
                begin
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