Page 341 - 완) I MDP 프로젝트 작품 보고서(전체과 1학년)1.6

• 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5V

tolerant
• Up to 11 timers
• Up to four 16 bit timers, each with up to 4 IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input
• 2 * 16 bit motor control PWM timers with dead-time generation and emergency stop
• 2 * watchdog timers (Independent and Window)
• SysTick timer : a 24-bit downcounter• 2 * 16-bit basic timers to drive the DAC
• Up to 13 communication interfaces

• Up to 2 * I2C interfaces (SMBus/PMBus)
• Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) • Up to 3
SPIs (18 Mbit/s), 2 with I2S interface multiplexed • CAN interface (2.0B Active)

• USB 2.0 full speed interface
• SDIO interface
• CRC calculation unit, 96-bit unique ID

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