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reg [31:0] tcnt;

always @(posedge clk)
if(!rst)
begin
speed1<=0;
speed2<=0;
speed3<=0;
end

else begin

if(tem1==1)
begin
speed1<=2'b01;
speed2<=2'b00;
speed3<=2'b00;
end
else speed1<=2'b00;

if(tem2==1)
begin
speed1<=2'b00;
speed2<=2'b01;
speed3<=2'b00;
end
else speed2<=2'b00;

if(tem3==1)
begin
speed1<=2'b00;
speed2<=2'b00;
speed3<=2'b01;
end
else speed3<=2'b00;
end

always @(posedge clk)
if(!rst) onoffout<=0;
else begin
if(onoffin==0)onoffout<=2'b00;
if(onoffin==1)onoffout<=2'b01;
end
endmodule
<Quartus II 핀 번호 >

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