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7 : step_phase2[3:0] <= 4'b1001;
endcase
if(flag1 == 1)
case(step3)

0 : step_phase2[3:0] <= 4'b1000;
1 : step_phase2[3:0] <= 4'b1100;
2 : step_phase2[3:0] <= 4'b0100;
3 : step_phase2[3:0] <= 4'b0110;
4 : step_phase2[3:0] <= 4'b0010;

5 : step_phase2[3:0] <= 4'b0011;
6 : step_phase2[3:0] <= 4'b0001;
7 : step_phase2[3:0] <= 4'b1001;
endcase
end

// 모터 3 상
always @(posedge clk)
begin
if(flag2 == 0)
case(step4)

0 : step_phase3[3:0] <= 4'b0001;
1 : step_phase3[3:0] <= 4'b0011;
2 : step_phase3[3:0] <= 4'b0010;
3 : step_phase3[3:0] <= 4'b0110;
4 : step_phase3[3:0] <= 4'b0100;

5 : step_phase3[3:0] <= 4'b1100;
6 : step_phase3[3:0] <= 4'b1000;
7 : step_phase3[3:0] <= 4'b1001;
endcase
if(flag2 == 1)

case(step5)
0 : step_phase3[3:0] <= 4'b1000;
1 : step_phase3[3:0] <= 4'b1100;
2 : step_phase3[3:0] <= 4'b0100;
3 : step_phase3[3:0] <= 4'b0110;

4 : step_phase3[3:0] <= 4'b0010;
5 : step_phase3[3:0] <= 4'b0011;
6 : step_phase3[3:0] <= 4'b0001;
7 : step_phase3[3:0] <= 4'b1001;
endcase

end
endmodule

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