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나. FPGA 에서 데이터 처리를 위한 프로그램 소스

module adc1(clk,rst,motor,led_red,led_blue,adc_clk,adc_ale,adc_start,adc_oe,adc_eoc,adc_input,
LCD_RS,LCD_RW,LCD_EN,DATA);
input clk,rst;
//ADC_input
input adc_eoc;
input [7:0] adc_input;
//ADC_output
output adc_clk, adc_oe,adc_ale,adc_start;
//LED_output
output led_red;
output led_blue;
//LCD_output
output LCD_RS, LCD_RW, LCD_EN;
output [7:0] DATA;
//MOTOR
output motor;
reg motor;
//LED_reg
reg led_red;
reg led_blue;
//ADC_reg
reg adc_clk, adc_oe, adc_ale, adc_start;
reg [7:0] adc_data, adc_time, clk_count;
reg [2:0] state_1;
//LCD_reg
reg LCD_RS, LCD_EN;
reg [2:0] state;
reg [4:0] clk_50, clk_100;
reg [7:0] DATA, line;
reg [27:0] clk_5;
//MOISTURE
reg [7:0] water;
//ADC_fsm
parameter IDLE = 3'b000;
parameter FS = 3'b001; // Function Set
parameter CD = 3'b010; // Clear Display
parameter DO = 3'b011; // Display On
parameter EM = 3'b100; // Entry Mode
parameter DISPLAY = 3'b101;
parameter WAIT = 3'b110;
parameter [1:0] START =2'd0, EOC=2'd1, OE= 2'd2, DATA_OUT =2'd3;

integer one, two, three;

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