Page 183 - 3-2

always @(posedge clk)
if(top_idle)
top_cnt<=0;
else
begin
top_cnt<=top_cnt+16'd1;
if(top_cnt_max) top_state<=~top_state;
end

reg mid_state;
reg mid_up;

reg mid_sync_0;
always @(posedge clk) mid_sync_0<=~lm_mid;
reg mid_sync_1;
always @(posedge clk) mid_sync_1<=mid_sync_0;

reg [15:0] mid_cnt;

wire mid_idle = (mid_state==mid_sync_1);
wire mid_cnt_max = &mid_cnt;

always @(posedge clk)
if(mid_idle)
mid_cnt<=0;
else
begin
mid_cnt<=mid_cnt+16'd1;
if(mid_cnt_max) mid_state<=~mid_state;
end

reg bot_state;
reg bot_up;

reg bot_sync_0;
always @(posedge clk) bot_sync_0<=~lm_bot;
reg bot_sync_1;
always @(posedge clk) bot_sync_1<=bot_sync_0;

reg [15:0] bot_cnt;

wire bot_idle = (bot_state==bot_sync_1);
wire bot_cnt_max = &bot_cnt;

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