Page 185 - 3-2

always @(posedge clk)
if(twou_idle)
twou_cnt<=0;
else
begin
twou_cnt<=twou_cnt+16'd1;
if(twou_cnt_max) twou_state<=~twou_state;
end

reg twod_state;
reg twod_up;

reg twod_sync_0;
always @(posedge clk) twod_sync_0<=~twod;
reg twod_sync_1;
always @(posedge clk) twod_sync_1<=twod_sync_0;

reg [15:0] twod_cnt;

wire twod_idle = (twod_state==twod_sync_1);
wire twod_cnt_max = &twod_cnt;

always @(posedge clk)
if(twod_idle)
twod_cnt<=0;
else
begin
twod_cnt<=twod_cnt+16'd1;
if(twod_cnt_max) twod_state<=~twod_state;
end

reg threed_state;
reg threed_up;

reg threed_sync_0;
always @(posedge clk) threed_sync_0<=~threed;
reg threed_sync_1;
always @(posedge clk) threed_sync_1<=threed_sync_0;
reg [15:0] threed_cnt;

wire threed_idle = (threed_state==threed_sync_1);
wire threed_cnt_max = &threed_cnt;

always @(posedge clk)

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