Page 210 - MDP2020-2

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204

end
end
end
end

always @(posedge clk, negedge rst)
begin
if(!rst)
begin
state_rxd <= 0;
end
else
begin
if(state_rxd == 0 && uart_rxd == 0)
begin
if(clk_cnt_ >= BAUD_CLK_WAIT)
begin
state_rxd <= 1;
end
else
begin
state_rxd <= 0;
end
end
else if(state_rxd == 1 && clk_cnt_ >= BAUD_CLK && rx_cnt == 8)
begin
state_rxd <= 0;
end
else
begin
state_rxd <= state_rxd;
end
end
end

always @(posedge clk, negedge rst)
begin
if(!rst)
begin
rx_cnt <= 0;
end
else
begin
if(state_rxd ==1 && clk_cnt_ >= BAUD_CLK)
begin
if(rx_cnt == 8)
begin
rx_cnt <= 0;