Page 212 - MDP2020-2

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end
else
begin
clk_cnt <= clk_cnt + 1;
clk_uart <= 0;
end
end
end

//bit count
always @(posedge clk, negedge rst)
begin
if(!rst)
begin
tx_cnt <= 0;
end
else
begin
if(clk_uart == 1 && tx_empty == 0)
begin
tx_cnt <= (tx_cnt + 1) % 10; //0 ~ 9
end
else
begin
tx_cnt <= tx_cnt;
end
end
end

always @(posedge clk, negedge rst)
begin
if(!rst)
begin
tx_out <= 1;
end
else
begin
if(clk_uart == 1)
begin
if(tx_cnt == 0)
begin
tx_out <= 0;
end
else if(tx_cnt < 9)
begin
//tx_reg
tx_out <= tx_reg[tx_cnt - 1];
end